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<title>CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values </title></head>
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<h1>CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>0F 5B /r CVTDQ2PS xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.</td></tr>
<tr>
<td>VEX.128.0F.WIG 5B /r VCVTDQ2PS xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1.</td></tr>
<tr>
<td>VEX.256.0F.WIG 5B /r VCVTDQ2PS ymm1, ymm2/m256</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert eight packed signed doubleword integers from ymm2/mem to eight packed single-precision floating-point values in ymm1.</td></tr>
<tr>
<td>EVEX.128.0F.W0 5B /r VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single-precision floating-point values in xmm1with writemask k1.</td></tr>
<tr>
<td>EVEX.256.0F.W0 5B /r VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single-precision floating-point values in ymm1with writemask k1.</td></tr>
<tr>
<td>EVEX.512.0F.W0 5B /r VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed single-precision floating-point values in zmm1with writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen packed single-precision floating-point values in the destination operand.</p>
<p>EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<p>VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.</p>
<p>VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmod-ified.</p>
<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
<h2>Operation</h2>
<p><strong>VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
                                         ; refer to Table 2-4
    ELSE
         SET_RM(MXCSR.RM);
                                         ; refer to Table 2-4
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] (cid:197)
              Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197)j * 32
    IF k1[j] OR *no writemask*
         THEN
              IF (EVEX.b = 1)
                    THEN
                         DEST[i+31:i] (cid:197)
              Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
                    ELSE
                         DEST[i+31:i] (cid:197)
              Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VCVTDQ2PS (VEX.256 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
DEST[159:128] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
DEST[MAX_VL-1:256] (cid:197) 0</pre>
<p><strong>VCVTDQ2PS (VEX.128 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>CVTDQ2PS (128-bit Legacy SSE version)</strong></p>
<pre>DEST[31:0] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] (cid:197) Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);</p>
<p>VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);</p>
<p>VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);</p>
<p>VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);</p>
<p>VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);</p>
<p>VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);</p>
<p>VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);</p>
<p>VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);</p>
<p>CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)</p>
<p>CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Precision</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instructions, see Exceptions Type 2;</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E2.</td></tr>
<tr>
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table></body></html>